A logic embedded DRAM has begun to expand its significant commercial applications into the field of digital appliances such as a digital TV, a DVD recorder, a digital still camera and the like, and has become an essential commodity item in the semiconductor industry. In case of a logic device, devices including gates in the order of tens of millions are integrated in one LSI by virtue of the 0.18 μm technology to thereby lead to the emergence of the SOC (system on chip) where various LSI's including CPU are accommodated on one silicon chip. The embedding technology needed for implementing the SOC enables each LSI to exhibit maximum performance and is required to be achieved by minimal processing steps.
A DRAM memory cell is placed at an intersection of a word line and a bit-line (digit line) crossing with each other in a grid pattern. This memory cell is formed of one selection transistor (NMOS transistor) and a capacitor (capacitance device) connected in series thereto. Namely, the DRAM memory cell is formed of two devices: one capacitor for storing charges (data); and one transistor serving as a switch for controlling input and output of the data. The capacitance device featuring such a DRAM cell structure is generally classified into two types. One is a stack capacitance cell, wherein multilayer capacitor units are disposed on the transistor to increase the overall electrode area. The other is a trench capacitance cell, wherein the capacitor is formed in a silicon substrate.
The trench capacitance cell has a good surface flatness, and is fairly compatible with a logic device fabrication process since a high temperature heat treatment such as an oxidation for a dielectric film formation or the like is carried out prior to a transistor formation. Further, in case of the trench capacitance cell, since a MOSFET formation process is started after a trench formation process is completed, the MOSFET formation process is hardly affected by the trench capacitance cell formation process. This is a merit of the trench cell in the DRAM embedding technology. On the other hand, it is disadvantageous in that a deeper trench needs to be formed to increase the storage capacitance since a high-K dielectric film cannot be used as a capacitor dielectric film. Moreover, a connection between the source/drain of the cell transistor and a capacitor electrode is getting more difficult with the scaling down of the device; and particularly, a processing beyond a 0.18 μm regime becomes very difficult. As a consequence, it is required to dig the trench deeply. This is referred to as a DT (Deep Trench: deep groove) technology.
A conventional built-in power MOSFET formed on a surface of a silicon substrate utilizes only an extremely small area on the surface of the substrate to thereby put a limitation in reducing an electrode gap since a high voltage applied thereto needs to be controlled, resulting in hampering the lowering of the on-resistance. In the DT technology, however, a trench (a groove) is formed in the silicon substrate to form the MOSFET three-dimensionally, and the electrode gap needed for a high voltage control is provided in the depth direction such that a device pitch can be reduced while maintaining a device withstand voltage of several tens of V.
In the DT (groove or hole) processing, particularly, an aspect ratio (a ratio between a length and a breadth of groove or hole) and a cross sectional shape become matters of primary concern. In this case, it is preferable that the aspect ratio is at least 10; and, as for the cross sectional shape, it is ideal that a sidewall portion thereof is of a smooth plane, a tilt angle of which is about 0 degree (perpendicular), and a bottom portion is of a semicircular recessed shape (bottom round). As mentioned above, in the DT, very highly advanced and accurate anisotropic etching is required. Here, the bottom round is to facilitate an insulating film burying process to be performed subsequently. Further, a taper angle may be added to a tilt angle in the sidewall portion to facilitate the processing in case a deposition film coverage becomes deteriorated in the insulating film burying process.
As a kind of such a trench processing technology on the silicon wafer, there is a plasma etching method, wherein an anisotropic plasma etching is performed on a single crystalline silicon layer by using, e.g., a silicon nitride film as a mask. In this case, a very small amount of oxygen (O2) gas is added to an etching gas containing halogen, e.g., chlorine (Cl2) gas or hydrogen bromide (HBr) gas, such that an etching is carried out by using Cl2 or HBr; and SiCx and SiBrx as etching reaction products are oxidized by the supply of O2 to become SiO2, which is deposited on the sidewall of an etching part, thereby providing a protection thereto against the etching.
However, since the single crystalline has no base layer to stop etching, if an etching rate in a central part of the wafer is different from that in an outer periphery thereof (outer margin), in-surface uniformity of the wafer along the depth of the trench becomes deteriorated. Particularly, a large amount of reaction products will be deposited on the outer periphery of the wafer; and the etching rate along the depth direction becomes inevitably decreased as the etching progresses. The reason for this is that the range of an incident angle of radicals reaching to a bottom portion of a part to be etched becomes narrower as the trench gets deeper, and thus, a radical density becomes lowered.
Meanwhile, for performing a plasma etching on the silicon wafer, a ring member 13 called as a focus ring or the like is practically provided on a susceptor 11 to surround a periphery of a silicon wafer 12, as shown in FIG. 6. The focus ring 13, made of an insulating material, e.g., quartz or the like, functions to adjust a shape of plasma in the vicinity of a periphery (peripheral edge) of the silicon wafer. A surface of the focus ring 13 is uniformly mirror-finished. If the surface of the focus ring 13 is rough, reaction products are deposited, and deposits thereof float upwardly to be adhered on a backside or a side of the wafer W. Here, the present inventors have found that the in-surface uniformity in depth of a trench is deteriorated at the outer periphery of the wafer since a large amount of reaction products are deposited, and therefore, the focus ring has to be mirror-finished.
As a trench processing technology using a plasma, reference 1 has been known. Reference 1 discloses that a trench processing using a gaseous mixture as a processing gas is performed on a silicon by using a silicon oxide film as a mask, wherein the gaseous mixture is made of HBr (hydrogen bromide) gas as a main component, SF6 (sulfur hexafluoride), SiF4 (Tetrafluorosilane), He (helium) gas and O2 (oxygen) gas. However, reference 1 cannot resolve the aforementioned objects.
Reference 1: Japanese Patent Laid-open Application No. H11-135489.